Technical Design Report for the Phase-II Upgrade of the ATLAS TDAQ System

Abstract

This Technical Design Report documents the plans to upgrade the ATLAS Trigger and Data Acquisition system for the High Luminosity LHC (HL-LHC). The HL-LHC is expected to start operations in the middle of 2026, to ultimately reach a peak instantaneous luminosity of "L = 7.5\times 10^{34} cm^{-2}s^{-1}", corresponding to approximately 200 inelastic proton-proton collisions per bunch crossing, and to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined (up to 4000 fb"^{-1}"). Meeting these requirements poses significant challenges to the Trigger and to the Data Acquisition system to fully exploit the physics potential of the HL-LHC. A baseline architecture, based on a single-level hardware trigger with a maximum rate of 1 MHz and 10 ms latency, is proposed and documented. With the help of a hardware-based tracking subsystem as co-processor, software-based reconstruction follows to achieve further rejection. Up to 10 kHz event data are sent into storage. The Report describes in detail the physics motivations, the requirements, the fundamental parameters, the technical design implementation, and the expected performance of the proposed upgrade. The Report also documents the organisation of the Upgrade Project, its management structure, planning and scheduling with a review of the major milestones, and costing information.