Interaction of Formal Design Systems in the Development of a Fault-Tolerant Clock Synchronization Circuit

Simple item page
dc.contributor.authorMiner, Paul; Pullela, Shyamsundar; Johnson, Steven
dc.date.accessioned2025-11-05T20:34:43Z
dc.date.available2025-11-05T20:34:43Z
dc.date.issued1994-05
dc.identifier.urihttps://hdl.handle.net/2022/34244
dc.relation.ispartofseriesIndiana University Computer Science Technical Reports; TR405
dc.rightsThis work is protected by copyright unless stated otherwise.
dc.rights.uri
dc.titleInteraction of Formal Design Systems in the Development of a Fault-Tolerant Clock Synchronization Circuit

Files

Original bundle

Now showing 1 - 1 of 1
Thumbnail Image
Name:
TR405.pdf
Size:
194.24 KB
Format:
Adobe Portable Document Format
Download

Collections

Technical Reports
Can’t use the file because of accessibility barriers? Contact us