Matrix Chain Ordering in Polylog Time with n/lg n Processors
| dc.contributor.author | Bradford, Phillip; Rawlins, Gregory; Shannon, Gregory | |
| dc.date.accessioned | 2025-11-04T18:30:00Z | |
| dc.date.available | 2025-11-04T18:30:00Z | |
| dc.date.issued | 1992-12 | |
| dc.identifier.uri | https://hdl.handle.net/2022/34205 | |
| dc.relation.ispartofseries | Indiana University Computer Science Technical Reports; TR369 | |
| dc.rights | This work is protected by copyright unless stated otherwise. | |
| dc.rights.uri | ||
| dc.title | Matrix Chain Ordering in Polylog Time with n/lg n Processors |
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